Panasonic MN103S

Chapter 3
Clock Generator
Control Registers III - 3
3.2 Control Registers
3.2.1 Clock Generator Control Register
Table:3.2.1 shows the internal clock supply.
Table:3.2.1 Clock Generator Control Register
3.2.2 PLL Control Registers
■ PLL Control Register (PCNT: 0x0000AFF2) [8, 16-bit Access Register]
Register Address R/W Access size Description Page
Clock generator
PCNT 0x0000AFF2 R/W 8, 16 PLL control register III-3
CKCTR 0x00008280 R/W 8, 16 Clock control register III-5
R/W Readable / Writable
R Readable
WWritable
bp 1514131211109876543210
Flag ----------
PLL
SEL
-
PLL
ON
-
CK
SEL1
CK
SEL0
At reset0000000000000000
AccessRRRRRRRRRRR/WRR/WRR/WR/W
bp Flag Description Set condition
15-6 - - -
5 PLLSEL Select the PLL output
0: Oscillation clock (OSCI)
1: PLL output
4-- -
3 PLLON Set the PLL ON/OFF
0: PLL ON
1: PLL OFF
2-- -
1-0
CKSEL1
CKSEL0
Select the PLL multiplication ratio of
oscillation frequency
00: 4 multiplication of oscillation frequency
01: 6 multiplication of oscillation frequency
10: 8 multiplication of oscillation frequency
11: Setting prohibited
When changing the PLLON flag and the CKSEL[1:0] flag of the
PCNT register, the PLLSEL flag must be set to "0".
And then, set the PLLSEL flag to "1" after waiting for more than
200 µs