Panasonic MN103S

Chapter 10
Motor Control PWM
X - 18 Control Registers
10.2.11 PWM Pin Protection Control Registers
This register is used to automatically bring the PWM output pins into high impedance state by the specified inter-
rupt generation. The output pins can return from high impedance state by clearing the interrupt request flag (IR).
This register needs to be set only when single-buffer mode is selected.
■ PWM Pin Protection Control Register (PWMOFF: 0x0000A360) [8,16-bit Access Register]
..
The TM11 output protection can be put into the high impedance state by setting the port 7 I/O
control register (P7DIR) to input mode.
..
bp 1514131211109876543210
Flag
-- - -
IRQS
EL12
IRQS
EL11
IRQS
EL10
IRQS
EL02
IRQS
EL01
IRQS
EL00
-
CLR
HZ1
CLR
HZ0
-
USE
HZ1
USE
HZ0
At reset0000000000000000
Access R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
bp Flag Description Setting condition
15 - - -
14-12 - Reserved Set to “000”.
11-9
IRQSEL12
IRQSEL11
IRQSEL10
PWM1 protection interrupt selection ( which interrupt
the pin is to be protected)
000: IRQ0
001: IRQ1
010: IRQ2
011: IRQ3
100: IRQ4
101: IRQ5
11X: Setting prohibited
8-6
IRQSEL02
IRQSEL01
IRQSEL00
PWM0 protection interrupt selection ( which interrupt
the pin is to be protected)
000: IRQ0
001: IRQ1
010: IRQ2
011: IRQ3
100: IRQ4
101: IRQ5
11X: Setting prohibited
5 - Reserved Set to “0”.
4 CLRHZ1
PWM1 output protection function 0: Disabled
1: Enabled
3 CLRHZ0
PWM0 output protection function 0: Disabled
1: Enabled
2 - Reserved Set to “0”.
1 USEHZ1
PWM1 output setting 0: PWM output in high impedance state
1: PWM output
0 USEHZ0
PWM0 output setting 0: PWM output in high impedance state
1: PWM output