Panasonic MN103S

Chapter 10
Motor Control PWM
Control Registers X - 7
10.2.3 PWM Output Polarity Control Registers
PWM output polarity control register selects polarity for each of the PWM outputs.
This register can select double-buffer or single-buffer mode by the SDSELAn flag of the PWM mode control reg-
ister (PWMMDn). When double-buffer mode is selected, the value of OUTMDn is loaded into the register at the
timing selected with PWMMDn register. When the PWM counter is not running, the double-buffer value is
loaded into the register as is regardless of the specified read timing; thus, ensuring smooth use of double buffer
from the initial state where the PWM counter starts.
■ PWM0 Output Polarity Control Register (OUTMD0: 0x0000A304) [8,16-bit Access Register]
bp 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Flag
----------
PXD
TNW
0
PXD
TW0
PXD
TNV
0
PXD
TV0
PXD
TNU
0
PXD
TU0
At reset 0000000000000000
Access RRRRRRRRRRR/WR/WR/WR/WR/WR/W
bp Flag Description Setting condition
15-6 - - -
5PXDTNW0
Output polarity for NPWM02 0: Positive phase
1: Negative phase
4PXDTW0
Output polarity for PWM02 0: Positive phase
1: Negative phase
3 PXDTNV0
Output polarity for NPWM01 0: Positive phase
1: Negative phase
2 PXDTV0
Output polarity for PWM01 0: Positive phase
1: Negative phase
1 PXDTNU0
Output polarity for NPWM00 0: Positive phase
1: Negative phase
0PXDTU0
Output polarity for PWM0 0: Positive phase
1: Negative phase