Panasonic MN103S

Chapter 8
8-bit Timer
Overview VIII - 7
8.1.3 Block Diagram
■ 8-bit Timer Block Diagram
Figure:8.1.4 8-bit Timer Block Diagram
Timer n
( n = 0, 1, 2, 3, 4, 5, 6, 7, 14, 15, 16, 17)
TMnBR
TMnBC
TMnIN0
TMnIN1
TMnIN2
Underflow
Reload
Load
TMnCI
NTMIRQn
TMOUTn
Lower timer
casucading signa
Under flow interrupt
Timer output
Count operation enable
Reset
Base register
Binary counter
T
R
Q
TMnIN7
:
TMnMD
Mode register
-
-
-
CNE
LDE
CK2
CK1
CK0
M
U
X