Chapter 2
CPU Basics
II - 4 Block Diagram
Table:2.2.1 Block Diagram and Function
Blocks Description
Clock generator
Uses a clock oscillator circuit driven by an external crystal or ceramic resonator to supply clock signals
to CPU blocks.
Program counter
Generates addresses for the instructions to be inserted into the instruction queue. Normally
incremented by sequencer indication, but may be set to branch destination address or ALU operation
result when branch instructions or interrupts occur.
Instruction queue Stores the instructions up to execution.
Instruction decoder
Decodes the instruction queue, sequentially generates the control signals needed for instruction
execution, and executes the instruction by controlling the blocks within the chip.
Instruction
execution controller
Controls CPU block operations in response to the result decoded by the instruction decoder and
interrupt requests.
Extension function
Executes extended instructions such as high-speed multiplication and multiply and accumulate opera-
tion instructions.
AU Executes arithmetic operations.
LU Executes logic operations.
Barrel shifter Executes shift operations.
IInternal ROM, RAM Assigned to the execution program, data and stack region.
Address register
Be used as address pointers and supports the operation instructions (addition, subtraction, and com-
parison) involved in address calculations.
Data register Can use generally for all operations.
Interrupt control Detects interrupt requests from peripheral functions, requests CPU shift to interrupt processing.
Bus control
Controls connection of CPU internal bus and CPU external bus. Includes bus usage arbitration
function.
Internal peripheral functions
Includes peripheral functions (A/D converter, 3-phase PWM, serial I/F, 8-bit timer, 16-bit timer).
Peripheral functions vary depending on the model.
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