Chapter 3
Clock Generator
III - 2 Overview
3.1 Overview
The clock generator has an internal PLL circuit and supplies a frequency that is a multiple of the oscillating fre-
quency of the oscillator to this microcontroller and peripheral circuit.
3.1.1 Functions
Table.3.1.1 shows the functions of the clock generator.
Table:3.1.1 Functions of Clock Generator
3.1.2 Block Diagram
Figure:3.1.1 Block Diagram of Clock Generator
Functions Description
Oscillation support Self-excited / externally excited oscillation
Oscillating frequency Maximum: 15.0MHz
System clock (MCLK))
Supplies 1/2, 1, 1.5, 2, 3, 4, 6 and 8 multiplication of the oscillating fre-
quency (Maximum 60.0 MHz)
Peripheral clock (LOCLK)
Supplies 1/4, 1/2, 0.75, 1, 1.5, 2, 3 and 4 multiplication the oscillating
frequency (Maximum 30.0 MHz)
PLL
OSCOOSCI
MCLK
PCNT
OSCI
PLLOUT
CKCTR
IOCL
Selctor
Selctor
Frequency
divide
circuit
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