Chapter 5
Interrupt Controller
Control Registers V - 9
5.2.2 Processor Status Word
■ Processor Status Word
The interrupt enable flag and interrupt mask level flag are used as interrupt-related flags in the processor status
word (PSW). These flags are read- and write-enabled flags. For information about the PSW, refer to [Chapter 2
CPU].
Table:5.2.2 Processor Status Word
Table: 5.2.3 shows the relationship between interrupt mask levels and acceptable interrupt levels.
Table:5.2.3 Relationship between Interrupt Mask Levels and Interrupt Levels that Can be Accepted
bp 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Flag --S1S0IEIM2IM1IM0----VCNZ
At reset 0000000000000000
Access R R R/W R/W R/W R/W R/W R/W R R R R R/W R/W R/W R/W
bp Flag
Description Set condition
15-12 - - Refer to[ Chapter 2 CPU ]
11 IE
Interrupt enable 0: disabled
1:enabled
This flag allows all interrupts to be accepted except for reset interrupts
and non-maskable interrupts. When an interrupt is accepted, IE flag is
cleared to “0” (interrupt disabled). Set IE flag to “1” when accepting
multiple interrupts within the interrupt processing program.
10-8
IM2
IM1
IM0
Interrupt mask level Specifies the interrupt mask level. When IE flag is “1”, the CPU core
accepts the interrupt with level higher than the mask level.
7-0 - - Refer to [ Chapter 2 CPU ]
Interrupt mask level
Acceptable interrupt level
IM2 IM1 IM0
0 0 0 Interrupt disabled (only non-maskable interrupts
accepted.)
001 0
010 0 to 1
011 0 to 2
100 0 to 3
101 0 to 4
110 0 to 5
111 0 to 6
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