Chapter 6
ROM Correction
ROM Correction Operation VI - 13
6.3.2 ROM Correction Setting Example
■ ROM Correction Setting Example (1)
8 bytes of data stored in the internal ROM addressees “0x40002000 ~ 0x40002007” are corrected by ROM cor-
rection channel 0 as indicated in the following.
Lower 3 bits Before change After change
0x40002000 0 0x00 → 0x00
+1 1 0x00 0x11
+2 2 0x00 0x22
+3 3 0x00 0x33
+4 4 0x00 0x44
+5 5 0x00 0x55
+6 6 0x00 0x66
+7 7 0x00 0x77
Setup Procedure Description
(1) Confirm ROM correction status
RCRCTR (0x7FF00000)
bp3: RCMEN=0
bp2: RCCEN=0
bp0: RCRWE=0
(1) Confirm that the ROM correction control register
(RCRCTR) is set to “0x00” (ROM correction enable).
When it is set to “0x04” (ROM correction enable), reset
ROM correction.
(2) Set a register write enabled
RCRCTR (0x7FF00000)
bp3: RCMEN=0
bp2: RCCEN=0
bp0: RCRWE=1
(2) Write “0x01” to the RCRCTR register to set the ROM
correction address register (RCR0AR) and the ROM
correction data register (RCR0DR) write enabled.
(3) Set the RCR0AR register
RCR0AR (0x7FF00100)
bp19-0: RC0AD19-0=0x02000
bp31: RC0CEN=1
(3) Set the lower 20 bits of the first address subject to ROM
correction in bp19~bp0 of the RCR0AR register and
theRC0CEN flag to “1” in bp31.
(4) Set the RC0DR register
RCR0DR (0x7FF00138)
= 0x7766554433221100
bp63-0: RC0DT63-0
=0x7766554433221100
(4) Set 8 bytes of data (0x7766554433221100) used for
ROM correction to the RCR0DR register.
(5) Set ROM correction enabled (5) Write “0x04” to the RCRCTR register to enable ROM
correction.
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