Panasonic MN103S

Chapter 5
Interrupt Controller
V - 2 Overview
5.1 Overview
The interrupt controllers are comprised of reset interrupts, non-maskable interrupts (NMI), 9 external interrupt
pins, and 45 internal interrupts (peripheral function interrupts).
5.1.1 Functions
Table:5.1.1 Interrupt Functions
Interrupt type Reset interrupt Non-maskable interrupt Level interrupt
Starting address
0x40000000 0x40000008 0x40000000+ interrupt
Value of vector table
Interrupt level
- - Can be set levels from 0 to 6 by
program
Interrupt factor count
1 2 9 (external pin input)
31 (internal peripheral function)
Interrupt factor
External RST pin input
Software reset
Power supply voltage
detection reset
Watchdog timer overflow interrupt
System error interrupt
External pin input,
Interrupts by internal peripheral
function
Generated (request)
operation
Direct input to CPU core Input to the CPU core from the
NMICR register
Input the interrupt highest priority
level to the CPU core by GnICR
register.
Accept operation
Always accepts Always accepts Acceptance by the processor sta-
tus register (PSW) and interrupt
control register (GnICR).
Machine cycles until
accepted
Refer to [11.3.1 Oscillation
Stabilization Wait Opera-
tion]
Up to 14 cycles Up to 14 cycles
PWM status after
acceptance
All flags are cleared to “0”. The interrupt mask level of PSW
is cleared to “000”.
Values of the interrupt level flag are
set to the interrupt mask level in
PSW (masking all interrupt
requests with the same or the lower
priority)