Panasonic MN103S

Chapter 16
Appendix
XVI - 38 Extension Instruction Specification
16.4 Extension Instruction Specification
16.4.1 Arithmetic extension function
■ Arithmetic Extension Function
The block diagram is shown below in which extension arithmetic units are connected to this series CPU core.
With the MN103S00 Series, multipliers capable of 32 × 32 multiply operation, multiply and accumulate
arithmetic units capable of 32 × 32 + 64 multiply and accumulate operation, priority encoders and saturation
compensation arithmetic units are incorporated as standard. Extension instructions using such extension
arithmetic units are described in this section.
Figure:16.4.1 Block Diagram of the Extension Arithmetic Units
Arithmetic
extension
section A
Arithmetic
extension
section B
Program
counter
section
Instruction data Instruction address
Operand data
Operand address
Barrel
shifter
LU AU
Extension
arithmetic
unit A
Register
Instruction
decoding section
Microcontroller
core instruction
decoder
Instruction
queue
Extension
instruction
decoder A
Arithmetic extension interface
Extension
arithmetic
unit B
Extension
instruction
decoder B
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