Panasonic MN103S

Chapter 14
A/D Converter
Operation XIV - 27
14.3 Operation
14.3.1 A/D Converter Operation
■ A/D Converter Timing
Figure: 14.3.1 shows A/D converter timing. The conversion time of A/D converter is the total of the sampling
hold (S/H) time , 10 bit conversion time and transfer time. When S/H time is 1 cycle, conversion time is 12 con-
version clock cycles. When S/H time is 4 cycles, conversion time is 15 conversion clock cycles.
Figure:14.3.1 A/D Converter Timing (S/H 1 Cycle)
■ Setting Clock for A/D Converter
A/D conversion clock can be selected from 1, 2, 3, 4, 8 and 16 dividing of IOCLK. However, it have to be
selected so that the conversion time is over 1.0µs and S/H time is over 200ns. The following table shows the con-
version time at IOCLK=30MHz.
The conversion clock should be selected from 2, 3, 4, 8, and 16 dividing at IOCLK=30MHz.
Table:14.3.1 A/D Conversion Time
Set value A/D converter time
Conversion clock
(cycle)
S/H cycle S/H time 10 bit conversion time Transfer time Total
IOCLK × 3
(100 ns)
2 cycles 200 ns
1 cycle × 10 bits
(1.0 µs)
1 cycle
(100 ns)
13 cycles
(1.3 µs)
IOCLK × 2
(66.7 ns)
4 cycles 267 ns
1 cycle × 10 bits
(667 ns)
1 cycle
(66.7 ns)
15 cycles
(1.0 µs)
IOCLK: 30 MHz
S/H bp9 bp8 bp7 bp6 bp5 bp4 bp3 bp2 bp1 bp0 Transfer
S/H
bp9 bp8
-Interrupt generation
-Write to a register
At continuous converi
o
Status
Conversion
clock
Start