Panasonic MN103S

Chapter 11
Watchdog Timer
Overview XI - 3
11.1.2 Block Diagram
■ Watchdog Timer Block Diagram
Figure:11.1.1 Watchdog Timer Block Diagram
OSCI
NRST
8-bit binary counter
Oscillation
stabilization
wait release
Control register
Interrupt counter
Reset
8
1/2
10
1/2
12
1/2
14
1/2
16WDBC
WDCTR
Reset
16-bit binary counter
Reset
Clock source
selection
Internal reset
generation
RSTCTR register
Internal reset signal
1/2
SYSCLK
Binary counter
interrupt
WD0VFIRQ
Hard reset signal