Panasonic MN103S

Chapter 12
Serial interface 0 and 1
Overview XII - 3
12.1.2 Block Diagram
■ Serial Interface 0 and 1 Block Diagram
Figure:12.1.1 Serial Interface 0 and 1 Block Diagram
Reception shift register
Reception register Transmission register
SBOn
SCnRIRQ
SBIn
IRQ control circuit
Transmission control circuit
Clock control circuit
SBTn
Parity bit control circuit
SCnSTR
SCnCTR
SCnTIRQ
0
7
SC0OE
SC0PE
SC0FE
SC0RBSY
SC0TBSY
SC0RXA
SC0TBF
SC0LN
SC0S0
SC0PTY1
SC0PTY0 SC0PTY2
SC0SB
0
7
SC0TEN
SC0BRE
SC0REN
SC0PTL
8
15
SC0S1 SC0OD
1/161/2
SCAnOD
Stop bit detection circuit
Overrun error detection
Read/Write Read/Write
EXCLK. (Timer output etc.)
RB-SFT
SCnRB
SCnTB
SWAP MSB<->LSB
SCAnPTY0 SCAnPTY1 SCAnPTY2
BUSY generation circuit
Reception bit counter
Transmission bit counter
Transmission data control state machine
Selector