Panasonic MN103S

Chapter 1
Overview
Hardware Functions I - 3
1.2 Hardware Functions
CPU Core MN103S core
4 GB of linear address space (for instructions / data)
LOAD/STORE architecture with 5-stage pipeline
46 basic instructions + 30 extension instructions
6 addressing modes
Instruction set of 1 byte in word length
Extension arithmetic unit incorporated (high-speed multiply, multiply and accumulate and
saturation operation instructions)
Machine cycle: 16.7 ns (oscillation frequency: 10 MHz, 6 multiply)
Operation mode: Normal mode
Oscillation Circuit Self-excited/externally excited oscillation
ROM Collection Maximum 4 parts in a program
Internal Memory MN103SA7D ROM 64Kbytes RAM 4Kbytes
MN103SA7G ROM 128Kbytes RAM 4Kbytes
MN103SFA7K ROM 256Kbytes RAM 8Kbytes
Interrupts Internal interrupts: 47 interrupts
Watchdog timer overflow interrupts
System error interrupts
<Timer Interrupts>
Timer 0 underflow interrupts
Timer 1 underflow interrupts
Timer 2 underflow interrupts
Timer 3 underflow interrupts
Timer 4 underflow interrupts
Timer 5 underflow interrupts
Timer 6 underflow interrupts
Timer 7 underflow interrupts
Timer 8 overflow/underflow interrupts
Timer 8 compare/capture A interrupts
Timer 8 compare/capture B interrupts
Timer 9 overflow/underflow interrupts
Timer 9 compare/capture A interrupts
Timer 9 compare/capture B interrupts
Timer 10 overflow/underflow interrupts
Timer 10 compare/capture A interrupts
Timer 10 compare/capture B interrupts
Timer 11 overflow/underflow interrupts
Timer 11 compare/capture A interrupts
Timer 11 compare/capture B interrupts
Timer 12 overflow/underflow interrupts
Timer 12 compare A interrupts
Timer 12 compare B interrupts
Timer 13 overflow/underflow interrupts
Timer 13 compare A interrupts
Timer 13 compare B interrupts
Timer 14 underflow interrupts
Timer 15 underflow interrupts