Panasonic MN103S - Serial Interface Control Registers

Chapter 12
Serial interface 0 and 1
XII - 6 Control Registers
12.2.3 Serial Interface Control Registers
The serial control register is used to set the operation conditions for the corresponding serial interface. This regis-
ter controls parameters including clock source selection, parity bit selection, protocol selection and enabling of
transmission and reception.
■ Serial 0 Control Register (SC0CTR: 0x0000A100) [8,16-bit Access Register]
bp 1514131211109876543210
Flag
SCA0
TEN
SCA0
REN
SCA0
BRE
Rese
rved
SCA
0PTL
Rese
rved
SCA
0OD
Rese
rved
SCA
0LN
SCA
0PT
Y2
SCA
0PT
Y1
SCA
0PT
Y0
SCA
0SB
-
SCA
0S1
SCA
0S0
At reset 0 0 0 0000000000000
Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W
bp Flag Description Setting condition
15 SCA0TEN
Transmission enable 0: Transmission disabled
1: Transmission enabled
14 SCA0REN
Reception enable 0: Reception disabled
1: Reception enabled
13 SCA0BRE
Break transmission 0: No break
1: Break
12 Reserved Reserved Always set this bit to “0”
11 SCA0PTL
Protocol 0: Start-stop (UART)
1: Synchronous
10 Reserved Reserved Always set this bit to 0”
9SCA0OD
Transmission/reception bit sequence 0: LSB first
1: MSB first
8 Reserved Reserved Always set this bit to “0”
7SCA0LN
Character length 0: 7 bits
1: 8 bits
6-4
SCA0PTY2
SCA0PTY1
SCA0PTY0
Parity bit 000: No parity
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Fixed at 0 (“L” output)
101: Fixed at 1(“H” output)
110: Even (even number of 1s)
111: Odd (odd number of 1s)
3SCA0SB
Stop bit 0: 1 bit
1: 2 bits
Stop bit selection is valid only in start-stop mode
1 bit judgement at reception
2-- -
1-0
SCA0S1
SCA0S0
Clock source 00: SBT0
01: 1/2 of timer n underflow frequency
10: Setting prohibited
11: 1/16 of timer n underflow frequency
1/2 of timer n underflow is not available in start-stop mode.