Panasonic MN103S - Programmable Timer Registers

Chapter 9
16-bit Timer
Control registers IX - 13
9.2.3 Programmable Timer Registers
Timer 8 to timer 11 each have 16-bit programmable timer registers. Programmable timer registers are composed
of the binary counter (TMnBC), the compare/capture A register (TMnCA) and the compare/capture B register
(TMnCB).
■ Timer 8 Binary Counter (TM8BC: 0x0000A210) [16-bit Access Register]
This is a binary counter of timers and a 16-bit readable only register. Table:9.2.2 shows updated timing (0x0000
clear, etc.) of the binary counter.
Table:9.2.2 The Updated Timing of Binary Counter and Update Value
bp 1514131211109876543210
Flag TM
BC15
TM
BC14
TM
BC13
TM
BC12
TM
BC11
TM
BC10
TM
BC9
TM
BC8
TM
BC7
TM
BC6
TM
BC5
TM
BC4
TM
BC3
TM
BC2
TM
BC1
TM
BC0
At reset 0000000000000000
Access RRRRRRRRRRRRRRRR
TMCLE flag (TMnMD)=0 TMCLE flag (TMnMD)=1
When initializing a timer (when the TMLDE
flag of the TMnMD register is set to “1”)
TMnBC←0x0000 TMnBC←0x0000
Count clock up (down) TMnBC←TMnBC+1
(TMnBC←TMnBC-1)
TMnBC←TMnBC+1
(TMnBC←TMnBC-1)
TMnBC overflow TMnBC←0x0000 TMnBC←0x0000
TMnBC underflow TMnBC←0xFFFF TMnBC←0xTMnCA
Count up (down) from the TMnBC and the
TMnCA match
TMnBC←TMnBC+1
(TMnBC←TMnBC-1)
TMnBC←0x0000
Count up (down) from the TMnBC and the
TMnCB match
No change No change
At the TMnCA capture No change TMnBC←0x0000
At the TMnCB capture No change No change