Panasonic MN103S

Chapter 2
CPU Basics
Programming Model II - 5
2.3 Programming Model
2.3.1 CPU Registers
The register set is divided into data registers that are used for arithmetic operations, etc., address registers that are
used for pointers, and a stack pointer. This arrangement contributes greatly to the improved performance of the
internal architecture, through reduction on instruction code size, improved parallelism in pipeline processing, etc.
This register enables programming in C and other high-level languages. The loop instruction register (LIR) and
the loop address register (LAR) are used to provide high-speed execution of branch instructions. High-speed loop
control is performed by loading the branch target instruction and following fetch address with the SETLB instruc-
tion and forming the loop using the Lcc instruction.
Figure:2.3.1 CPU Block Diagram
D0
D1
D2
D3
31 0
A0
A1
A2
A3
31 0
SP
PC
31 0
31
0
MDR
31
0
PSW
15 0
LIR
31
0
LAR
31
0
Data register
Address register
Stack pointer
Program counter
Multiply/divide register
Processor status register
Loop instruction register
Loop address register