Chapter 4
Bus Controller
Operation IV - 3
4.2 Operation
4.2.1 Operation of Bus Controller
■ Bus Configuration
The ROM bus between the CPU and internal ROM, the RAM bus between the CPU and internal RAM, the BC
bus between the CPU and bus controller, and the I/O bus between the bus controller and internal peripheral cir-
cuitry are available as the chip’s internal buses. The characteristics of each bus and the bus configuration are
shown in the following table and figure.
Table:4.2.1 Characteristics of Each Bus
Figure:4.2.1 Bus Configuration
Bus name Blocks Bus width Operating clock
ROM bus CPU to internal ROM 64 MCLK
RAM bus CPU to internal RAM 32 MCLK
BC bus CPU to BC 32 MCLK
I/O bus BC to internal I/O 32 IOCLK
Refer to chapter 3, “ Clock Generator” for MCLK and IOCLK.
Internal ROM
32
64
32
32
32
ROM bus
CPU core
RAM bus
Internal RAM
BC bus
Bus controller
I/O bus
I/O (peripheral)
Timers
Serial I/Fs
PWM
A/Ds
Address bus
Data bus
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