Panasonic MN103S

Chapter 4
Bus Controller
IV - 4 Operation
■ Data Access Timing
Data access to peripheral circuitry in the internal I/O space is performed in synchronization with IOCLK. Figure:
4.2.2 shows the data access timing chart of the internal I/O space. The address (ABIOA[30:0]), the chip select sig-
nal (NABIOCS[n]) and the read enable signal (NABIORE) are output simultaneously at the falling edge of
IOCLK(AKIOCLK), while the peripheral circuitry starts to drive the data onto the read data signal
(ABIORD[31:0]). The data on the read data signal is read simultaneously at the falling edge of IOCLK where the
access cycle is terminated.
Figure:4.2.2 Data Access Timing in the Internal I/O Space
■ Basic Bus Cycle Count
Refer to chapter 3 “ Clock Generator” for the frequency of MCLK and IOCLK.
Table:4.2.2 Relationship between Clock Frequency and Access Cycle Count (CPU Cycle)
Accessed destination MCLK (cycle count) IOCLK (cycle count)
Internal ROM
Instruction read 3 cycles -
Data read 3 cycles -
Internal RAM
Instruction read 4 cycles -
Data read/write 1 cycles -
Control register inside CPU
Read 3 cycles -
Write 2 cycles -
Control register outside CPU
(Control register space)
Read 3 cycles -
Write 2 cycles -
Internal I/O
(Internal I/O space)
Read (*2) 2 cycles I/O bus cycle
Write (*1)(*2) 1 cycles I/O bus cycle
(*!) : Each of all writes for the internal I/O is performed in 1 cycle by the use of the store buffer.
(*2) : Up to 3 cycles of synchronization wait occur.
The total of MCLK and IOCLK cycle count
AKIOCLK
ABIOA(30:0)
NABIOCS(n)
NABIORE
ABIOWD(31:0)
NABIOWE(3:0)
ABIORD(31:0)
Read cycle Write cycle
1 wait state1 wait state