Chapter 11
Watchdog Timer
XI - 2 Overview
11.1 Overview
This LSI has an internal 24-bit binary counter that can be used as a 16- to 24-bit watchdog timer. A watchdog
timer overflow can generate a non-maskable interrupt. And if an overflow occurs for the second time in a row
without clearing the binary counter of the watchdog timer, it is judged unable to return by software. Then, forced
hard reset will be executed.
The watchdog timer is also used as an oscillation stabilization wait timer.
11.1.1 Functions
Table: 11.1.1 shows watchdog timer functions.
Table:11.1.1 Watchdog Timer Functions
Watchdog timer
Interrupt source WDOVFIRQ
Bit count for the binary
counter
16, 18, 20, 22, and 24 bits
Overflow period 6.65 ms to 1677.72 (when the oscillation frequency is 10 MHz)
Oscillation stabilization
wait time
26.21 ms (when reset is released; when the oscillation frequency is 10 MHz)
Self-reset function The chip can be self-reset internally by writing to the RSTCTR register.
Forced-reset function Forced hard reset in case of an overflow generation for the second time in a row
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