Panasonic MN103S

Chapter 4
Bus Controller
IV - 2 Overview
4.1 Overview
The bus controller controls interfacing between the CPU and internal peripheral circuitry.
4.1.1 Functions
Table:4.1.1 shows the functions of the bus controller.
Table:4.1.1 Functions
4.1.2 Block Diagram
■ Bus Controller Block Diagram
The bus controller is comprised of a control section, CPU interface section and peripheral circuitry interface sec-
tion.
Figure:4.1.1 Bus Controller Block Diagram
Functions Description
Internal bus Provides high-speed control by means of the system clock (MCLK)
Store buffer
Avoids time penalty during storage operation by the store buffer of single stage
Supports for storage in the internal peripheral circuitry
When the store buffer is empty, storage operation is completed with no wait states,
and the CPU can execute successive processing
BC address bus
BC data bus
I/O address bus
I/O data bus
Core I/F signal
Peripheral circuitry I/F signal
BC control
section
Core I/F
Store buffer
Peripheral
circuitry I/F
BC internal address bus
BC internal data bus