Chapter 10
Motor Control PWM
X - 14 Control Registers
10.2.7 Dead Time Setting Registers
Dead Time setting register is used to set dead time of PWM0 and PWM1. Dead Time is designed to insert on time
delay into each of the upper and lower phases when the signal is inverted at PWM output. The dead time counter
functions in synchronization with clock set by the PWM mode control register ‘PWMMDn) and counts 1 every 2
clock cycles. The dead time or delay time is calculated with “setting × 2 + 1”. Thus, when “00” is set, 1 clock
cycle of dead time is inserted if dead time is enabled. This register needs to be set only when double-buffer mode
is selected. The value of DTMSETn is loaded into the register at the timing selected with the PWM mode control
register (PWMMDn). When the PWM counter is not running, the double-buffer value is loaded into the register as
is regardless of the specified read timing.
■ PWM0 Dead Time Setting Register (DTMSET0: 0x0000A31C) [8,16-bit Access Register]
■ PWM1 Dead Time Setting Register (DTMSET1: 0x0000A34C) [8,16-bit Access Register]
bp 1514131211109876543210
Flag
--------
DTS
T07
DTS
T06
DTS
T05
DTS
T04
DTS
T03
DTS
T02
DTS
T01
DTS
T00
At reset - - - - - - - -00000000
Access RRRRRRRRR/WR/WR/WR/WR/WR/WR/WR/W
bp Flag Description Setting condition
15-8 - - -
7-0
DTST07
to
DTST00
Setting PWM0 dead time Setting dead time value to 8-bit dead timer counter
bp 1514131211109876543210
Flag
--------
DTS
T17
DTS
T16
DTS
T15
DTS
T14
DTS
T13
DTS
T12
DTS
T11
DTS
T10
At reset - - - - - - - -00000000
Access RRRRRRRRR/WR/WR/WR/WR/WR/WR/WR/W
bp Flag Description Setting condition
15-8 - - -
7-0
DTST17
to
DTST10
Setting PWM1 dead time Setting dead time value to 8-bit dead timer counter
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