Panasonic MN103S

Chapter 8
8-bit Timer
Control Registers VIII - 13
8.2.3 Programmable Timer Registers
Timer 0 to timer 7,timer 14 to timer 17 each have 8-bit programmable timer registers.
Programmable timer registers consist of the base register and binary counter.
Timer n base registers set the initial value of the timer n binary counter (TMnBC) and the underflow period. The
value of timer n base register (TMnBR) setting is loaded into TMnBC under the following conditions:
• when the TMnLDE flag of the timer n mode register (TMnMD) = 1
• when an underflow occurs
Timer n binary counters are 8-bit readable registers. The counter values can be read.
■ Timer 0 Base Register (TM0BR: 0x0000A188) [8-bit Access Register]
■ Timer 1 Base Register (TM1BR: 0x0000A189) [8-bit Access Register]
■ Timer 2 Base Register (TM2BR: 0x0000A18C) [8-bit Access Register]
■ Timer 3 Base Register (TM3BR: 0x0000A18D) [8-bit Access Register]
bp 76543210
Flag TM0
BR7
TM0
BR6
TM0
BR5
TM0
BR4
TM0
BR3
TM0
BR2
TM0
BR1
TM0
BR0
At reset 00000000
Access R/W R/W R/W R/W R/W R/W R/W R/W
bp 76543210
Flag TM1
BR7
TM1
BR6
TM1
BR5
TM1
BR4
TM1
BR3
TM1
BR2
TM1
BR1
TM1
BR0
At reset 00000000
Access R/W R/W R/W R/W R/W R/W R/W R/W
bp 76543210
Flag TM2
BR7
TM2
BR6
TM2
BR5
TM2
BR4
TM2
BR3
TM2
BR2
TM2
BR1
TM2
BR0
At reset 00000000
Access R/W R/W R/W R/W R/W R/W R/W R/W
bp 76543210
Flag TM3
BR7
TM3
BR6
TM3
BR5
TM3
BR4
TM3
BR3
TM3
BR2
TM3
BR1
TM3
BR0
At reset 00000000
Access R/W R/W R/W R/W R/W R/W R/W R/W