Chapter 11
Watchdog Timer
XI - 10 Operation
11.3.3 Self-reset Operation
Self-reset operation is to reset the internal chip software.
■ Self-reset Operation
A self-reset is generated by setting the CHIPRST flag of the reset control register (RSTCTR) from “0” to “1”. A s
elf-reset is not operated if the CHIPRST flag set to “1” when it contains “1”. The CHIPRST flag retains the value
after the self-reset. The reset generated by the self-reset is an internal reset signal within the chip and does not
appear on the external reset pin. The oscillation stabilization wait is not operated.
11.3.4 Forced-reset Operation
■ Forced-reset Operation
If an overflow occurs for the second time in a row without clearing the binary counter of watchdog timer, it is
judged unable to return by software. And forced hard reset will be executed. After reset, the hard reset execute
oscillation stabilization wait operation again. However, it does not appear on the external reset pin.
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