Chapter 3
Clock Generator
Operation III - 7
3.3.2 Setup of Input Frequency
Input frequency range of clock generator is 5 MHz (minimum) and 15 MHz (maximum). When the input clock is
multiplied, the PLL output frequency (PLLOUT) needs to be set to be 40 MHz to 60 MHz. Table: 3.3.3 shows the
input frequency and PLL multiple magnification to be set.
Table:3.3.3 Setting of PLL Multiple Magnification for Input Frequency
3.3.3 Connection Example of Oscillator
Figure 3.3.1 shows basic configuration connected with a ceramic oscillator, and table 3.3.4 shows recommended
oscillators and the circuit constants.
Figure:3.3.1 Connection Example of Ceramic Oscillator
Table:3.3.4 Recommended Ceramic Oscillator and Circuit Constant
Input frequency PLL multiple magnification
4 multiplication 6 multiplication 8 multiplication
5 MHz Setting prohibited Setting prohibited 40 MHz
7 MHz Setting prohibited 42 MHz 56 MHz
8 MHz Setting prohibited 48 MHz Setting prohibited
10 MHz 40 MHz 60 MHz Setting prohibited
15 MHz 60 MHz Setting prohibited Setting prohibited
Frequency
[Hz]
Type
Ceramic oscillator
Product Number‘
Recommended circuit constant
Load Capacity
C1=C2 [pF]
External feedback resistor
Rx [Ω]
Dumping resistor
Rd [Ω]
5.000M
lead CSTLS5MOOG56-B0 (47) Open 0
SMD CSTCR5MOOG55-R0 (39) Open 0
7.000M
lead CSTLS7MOOG56-B0 (47) Open 0
SMD CSTCR7MOOG55-R0 (39) Open 0
8.000M
lead CSTLS8MOOG56-B0 (47) Open 0
SMD CSTCE8MOOG55-R0 (33) Open 0
10.000M
lead CSTLS10MOG56-B0 (47) Open 0
SMD CSTCE10MOG55-R0 (33) Open 0
15.000M SMD CSTCE15MOV53-R0 (15) Open 0
* ( ) shows capacity built into the oscillator.
R
x
R
d
RFB =1 MΩ
(typ)
OSCI
OSCO
C1
C2
Ceramic oscillation
Internal
feedback
resistor
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