Chapter 2
CPU Basics
II - 2 Overview
2.1 Overview
Table: 2.1.1 shows basic specifications.
Table:2.1.1 Basic Specifications
Structure
Load/store architecture
(9 registers)
Data: 32-bit x 4
Address: 32-bit x 4
Stack pointer: 32-bit x 1
Load/store architecture
(Others)
PC: 32-bit × 1
PSW : 16-bit × 1
Multiply/divide register: 32-bit x 1
Branch target register: 32-bit x 2
Instructions
Number of instructions 46
Addressing modes 6
Basic instruction length 1 byte
Code assignment
1 byte to 2 bytes (basic part) + 0 byte to 6
bytes (extension)
Basic performance
Maximum Internal operating frequency 60.0 MHz (External oscillation 10MHz)
Minimum instruction execution cycle 1 clock (16.7 nsec)
Inter-register operations 1 clock
Load/store 1 clock
Conditional branch 1 clock to 3 clock
Pipeline 5-stage (instruction fetch, decode, execution, memory access, write-back)
Address space 4 GB
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