Panasonic MN103S

Chapter 7
I/O Port
VII - 6 Overview
■ Block Diagram (P72, P73)
P72, P73 are dual-purpose that serve as 16-bit timer pins.
Figure:7.1.5 Block Diagram (P72 to P73)
■ Block Diagram (P52, P53, P54, P55, P56, P57)
P52 to P57 are dual-purpose ports that serve as PWM0 output pins.
Figure:7.1.6 Block Diagram (P52 to P57)
Internal data bus
P... indicates 1 bit of a register.
M
P
X
TM11IO0, TM11IO1
TM11IO0, TM11IO1
P72, P73
P7PLU
P7OUT
P7MD
P7DIR
P7IN
Internal data bus
P52 to P57
P5OUT
P5MD
P5DIR
P... indicates 1 bit of a register.
M
P
X
P5IN
M
P
X
PWM00, 01, 02
PWMHZ0
(PWM0 Hz control)
NPWM00, 01, 02
P5PLU