Chapter 7
I/O Port
Overview VII - 7
■ Block Diagram (P62, P63, P64, P65, P66, P67)
P62 to P67 are dual-purpose ports that serve as PWM1 output pins.
Figure:7.1.7 Block Diagram (P62 to P67)
■ Block Diagram (P90, P91, P92, P93, P94, P95, P96, P97,
PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7,
P90 to P97, PA0 to PA7 are dual-purpose ports that serve as AD input pins.
Figure:7.1.8 Block Diagram (P90 to P97, PA0 to PA7)
Internal data bus
P62 to P67
P6OUT
P6MD
P6DIR
P...
indicates 1 bit of a register.
M
P
X
P6IN
M
P
X
PWM10, 11, 12
PWMHZ1
(PWM1 Hz control)
NPWM10, 11, 12
P6PLU
P90
to
P97
PA0
to
PA7
PnMD
PnPLU
PnOUT
PnDIR
PnIN
Internal data bus
ADIN00 to 15
P...
indicates 1 bit of a register.
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