Panasonic MN103S

Chapter 8
8-bit Timer
VIII - 38 Event Count
8.6 Event Count
8.6.1 Operation
Event count operation is to count the rising edge of the TMnIO pin input as count clock.
■ Event Count Operation
When the TMnIO pin is selected to the clock source, the event counter operates. The event count operation means
that the binary counter (TMnBC) counts down the external signal input to the TMnIO pin. The underflow inter-
rupt request is generated at the binary counter underflow. The relationship between timers and event input pins is
shown below.
Table:8.6.1 TImer and Input Pin
■ Setting the Base Register
Set event count numbers that generate interrupts to the base register TMnBR.
Interrupt generation count number = TMnBR setting + 1
■ Count Timing of TMnIO pin input
TMnIO pin input is sampled by IOCLK. The rising edge of TMnIO pin input is counted, and the binary counter is
counted down. The pulse width should be IOCLK × 1.5 or more to detect the rising edge.
Figure:8.6.1 Count Timing of TMnIO Pin Input
Timer 0 Timer 1 Timer 2 Timer 3 Timer 4 Timer 5 Timer 6 Timer 7 Timer 14 Timer 15 Timer 16 Timer 17
Pulse output
pin
-TM1IO
pin
(P31)
TM2IO
pin
(P32)
TM3IO
pin
(P33)
TM4IO
pin
(P34)
TM5IO
pin
(P35)
-TM7IO
pin
(P51)
---TM17IO
pin
(P16)
Pin input
(TMnIO)
TMnLDE
flag
TMnCNE
flag
Base register
Binary counter
Interrupt request
fla
g
IOCLK
Sampling
NNN-1 01 00
N
Sampling Sampling