Panasonic MN103S

Chapter 6
ROM Correction
ROM Correction Control Registers VI - 7
6.2.4 ROM Correction Data Registers
Each of these registers specifies the correction data (channel number) used for ROM correction. Data can be writ-
ten only when the RCRWE flag in the ROM correction control register (RCRCTR) is “1”.
■ ROM Correction 0 Data Register (RCR0DR: 0x7FF00108) [32-bit access register]
bp 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48
Flag RC0
DT63
RC0
DT62
RC0
DT61
RC0
DT60
RC0
DT59
RC0
DT58
RC0
DT57
RC0
DT56
RC0
DT55
RC0
DT54
RC0
DT53
RC0
DT52
RC0
DT51
RC0
DT50
RC0
DT49
RC0
DT48
At reset xxxxxxxxxxxxxxxx
Access R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W
bp 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Flag RC0
DT47
RC0
DT46
RC0
DT45
RC0
DT44
RC0
DT43
RC0
DT42
RC0
DT41
RC0
DT40
RC0
DT39
RC0
DT38
RC0
DT37
RC0
DT36
RC0
DT35
RC0
DT34
RC0
DT33
RC0
DT32
At reset xxxxxxxxxxxxxxxx
Access R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W
bp 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Flag RC0
DT31
RC0
DT30
RC0
DT29
RC0
DT28
RC0
DT27
RC0
DT26
RC0
DT25
RC0
DT24
RC0
DT23
RC0
DT22
RC0
DT21
RC0
DT20
RC0
DT19
RC0
DT18
RC0
DT17
RC0
DT16
At reset xxxxxxxxxxxxxxxx
Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
bp 1514131211109876543210
Flag RC0
DT15
RC0
DT14
RC0
DT13
RC0
DT12
RC0
DT11
RC0
DT10
RC0
DT9
RC0
DT8
RC0
DT7
RC0
DT6
RC0
DT5
RC0
DT4
RC0
DT3
RC0
DT2
RC0
DT1
RC0
DT0
At reset xxxxxxxxxxxxxxxx
Access R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W
bp Flag Description Set condition
63-56
RC0DT63
to
RC0DT56
ROM correction 0 correction data Data of the address (lower 3bits set to 7) to be corrected
55-48
RC0DT55
to
RC0DT48
ROM correction 0 correction data Data of the address (lower 3bits set to 6) to be corrected
47-40
RC0DT47
to
RC0DT40
ROM correction 0 correction data Data of the address (lower 3bits set to 5) to be corrected
39-32
RC0DT39
to
RC0DT32
ROM correction 0 correction data Data of the address (lower 3bits set to 4) to be corrected
31-24
RC0DT31
to
RC0DT24
ROM correction 0 correction data Data of the address (lower 3bits set to 3) to be corrected
23-16
RC0DT23
to
RC0DT16
ROM correction 0 correction data Data of the address (lower 3bits set to 2) to be corrected
15-8
RC0DT15
to
RC0DT8
ROM correction 0 correction data Data of the address (lower 3bits set to 1) to be corrected
7-0
RC0DT7
to
RC0DT0
ROM correction 0 correction data Data of the address (lower 3bits set to 0) to be corrected