Panasonic MN103S - Page 142

Chapter 6
ROM Correction
VI - 6 ROM Correction Control Registers
■ ROM Correction 2 Address Register (RCR2AR: 0x7FF00120) [32-bit access register]
■ ROM Correction 3 Address Register (RCR3AR: 0x7FF00130) [32-bit access register]
bp 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Flag RC2
CEN
-----------RC2
AD19
RC2
AD18
RC2
AD17
RC2
AD16
At reset 000000000000xxxx
Access R/WRRRRRRRRRRRR/WR/WR/WR/W
bp 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Flag RC2
AD15
RC2
AD14
RC2
AD13
RC2
AD12
RC2
AD11
RC2
AD10
RC2
AD9
RC2
AD8
RC2
AD7
RC2
AD6
RC2
AD5
RC2
AD4
RC2
AD3
RC2
AD2
RC2
AD1
RC2
AD0
At rest xxxxxxxxxxxxxxxx
Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
bp Flag Description Set condition
31 RC2CEN
ROM correction channel 2 enabled 0: ROM correction disabled
1: ROM correction enabled
30-20 - - -
19-0
RC2AD19
to
RC2AD0
ROM correction channel 2 address These bits specify the lower 20 bits of the ROM address subject to
ROM correction. 8 bytes of data from the above ROM address to
(ROM address + 7) are subject to ROM correction.
bp 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Flag RC3
CEN
-----------RC3
AD19
RC3
AD18
RC3
AD17
RC3
AD16
At reset 000000000000xxxx
Access R/WRRRRRRRRRRRR/WR/WR/WR/W
bp 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Flag RC3
AD15
RC3
AD14
RC3
AD13
RC3
AD12
RC3
AD11
RC3
AD10
RC3
AD9
RC3
AD8
RC3
AD7
RC3
AD6
RC3
AD5
RC3
AD4
RC3
AD3
RC3
AD2
RC3
AD1
RC3
AD0
At reset xxxxxxxxxxxxxxxx
Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
bp Flag Description Set condition
31 RC3CEN
ROM correction channel 3 enable 0: ROM correction disabled
1: ROM correction enabled
30-20 - - -
19-0
RC3AD19
to
RC3AD0
ROM correction channel 3 address These bits specify the lower 20 bits of the ROM address subject to
ROM correction. 8 bytes of data from the above ROM address to
(ROM address + 7) are subject to ROM correction.