Panasonic MN103S

Chapter 13
Serial Interface 2
Overview XIII - 3
13.1.2 Block Diagram
■ Serial Interface 2 Block Diagram
Figure:13.1.1 Serial Interface 2 Block Diagram
Reception
shift register
SBO2
SC2RIRQ
SBI2
3
IRQ
SBT2
P
O
L
M
U X
SBO2
Transmission
shift register
MUX
M
U
X
M
U
X
SC2STR
SC2CTR2
SC2CTR1
SC2CTR0
SC2IOM
SC2TIRQ
0
7
SC2ERE
SC2ORE
SC2PEK
SC2FEF
SC2RBSY
SC2TBSY
SC2REMP
SC2TEMP
SC2IOM
SC2CMD
SC2SBIS
SC2SBOS
SC2SBTS
SC2CKM
0
7
SC2MST
SC2BRKF
SC2BRKE
SC2NPE SC2PM0 SC2PM1
SC2FM0 SC2FM1
0
7
1/16
SC2CE1 SC2STE
SC2DIR
SC2LNG0 SC2LNG1 SC2LNG2
0
7
SC2CKM
SC2CMD SC2MST
SC2CE1
SC2STE
SC2CMD
SC2FM0 SC2FM1
SC2SBTS
SC2SBOS
SC2SBIS
SC2RDB
SC2TRB
Reception
data buffer
SC2DIR
Read/Write
SC2RB
SC2TB
SWAP MSB<->LSB
- -
SC2CTR3
SC2PSC0 SC2PSC1 SC2PSC2
SC2PSCE
SC2FDC0 SC2FDC1
0
7
SC2NPE SC2PM0 SC2PM1
IOCLK
SIFCLK
Timer 14 Timer 15 Timer 16
MUX
Clock Selection
Clock
control
circuit
Transmission
bit counter
BUSY
generation
circuit
Reception
bit counter
Parity bit control circuit
Stop bit detection circuit
Break status
reception monitor
Overrun error detection
Start condition
generation circuit
Transmission control circuit
Transmission
data buffer
Start condition detection circuit
control
circuit