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Panasonic MN103S

Panasonic MN103S
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Chapter 11
Watchdog Timer
XI - 6 Control Registers
11.2.4 Reset Control Register
Reset control register is used to generate a self-reset (internal reset).
Reset Control Register (RSTCTR: 0x00008204) [8,16-bit Access Register]
bp 76543210
Flag
-------
CHIP
RST
At reset 00000000
Access RRRRRRRR/W
bp Flag Description Setting condition
7-1 - - -
0 CHIPRST
Self-reset (internal reset) A self-reset is generated when this flag is overwritten from “0” to “1”.
A self-reset is not generated if this flag is set to “1” when it contains
“1”. This flag value is retained even after the self-reset. The
CHIPRST flag is cleared either by an external reset signal or when
“0” is written to this flag by the program.

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