Panasonic MN103S

Chapter 4
Bus Controller
Operation IV - 5
■ Store Buffer
The bus controller has one store buffer (with a 32-bit data width) to avoid time penalty when conducting storage
operation in internal I/O. The CPU storage operation is completed when the address, data and access size are
stored in the store buffer, and is executed with no wait states. Writes from the store buffer to the internal I/O are
conducted in parallel with subsequent CPU operations. However, if there is a request from the CPU for loading or
storing to the internal I/O before writing from the store buffer is completed, execution of the request is delayed.
4.2.2 Internal ROM access control register
The internal ROM and internal flash memory can access in 2 cycles when the CPU clock (MCLK) is under 40
MHz.
Access cycle is set by the ROM access control register (ROMCTR).
■ Internal ROM Access Control Register (ROMCTR: 0x00008078) [16-bit Access Register]
bp 1514131211109876543210
Flag ----
Rese
rved
Rese
rved
ROM
WC1
ROM
WC0
---
Rese
rved
Rese
rved
Rese
rved
--
At reset0000001000000100
AccessRRRRR/WR/WR/WR/WRRRRRRRR
bp Flag Description Set condition
15-12 - - -
11-10 Reserved Reserved Always set “00”
9-8 ROMWC[1:0] Set the internal ROM access cycle count
00: Setting prohibited
01: 2 cycle(2 ×MCLK) access
If CPU clock (MCLK) becomes 40 MHz or over, it is prohibited.
10: 3 cycle(3 ×MCLK) access
When the CPU clock (MCLK) is 40 MHz or over, change an access
to the internal ROM to 3 cycle access (ROMMC[1:0]=10) by the
internal ROM access control register (ROMCTR) before the
PLLSEL flag of the PLL control register (PCNT) is switched from
"0" to "1".
The operation that is set to 2 cycle access is not guranteed.
11: Setting prohibited
7-5 - - -
4-2 Reserved Reserved Always set “001”
1-0 - - -