Panasonic MN103S

Chapter 11
Watchdog Timer
XI - 8 Operation
11.3.2 Watchdog Operation
The watchdog timer counts the oscillation frequency as a clock source. If the watchdog timer is overflowed, the
watchdog interrupt (WD0VFIRQ) is generated as a non-maskable interrupt (NMI). The watchdog timer control
register (WDCTR) sets when the watchdog timer is released and how long the time-out period should be.
■ Watchdog Timer Operation
When the watchdog timer is used, constant clear in program is needed to prevent an overflow of the watchdog
timer. The watchdog timer is executed to be cleared in the certain cycle on the correct code execution. As a result
of the software failure, the software cannot execute in the intended sequence; so, the watchdog timer is cleared in
the certain cycle. The watchdog timer overflows to detect errors.
■ Starting Watchdog Timer Operation and Watchdog Time-out Period
The watchdog binary counter is reset by setting the WDRST flag of the WDCTR register to “1”. The clock source
is selected by the WDCK2-0 flags of the WDCTR register. Table: 11.3.1 shows the set up values and types. The
watchdog time-out period is decided by the clock source.
The overflow period of the watchdog timer is calculated by the formula as follows.
Overflow period = 2
(16+WDCK
×
2)
/ fck [sec]
fck: Oscillation clock frequency
WDCK: WDCK[2:0]
The watchdog time-out period is generally decided from the execution time for main routine of program. The
watchdog timer operation is started by setting the WDCNE flag of the WDCTR register to “1”.
Table:11.3.1 Clock Source for Watchdog Timer and Overflow Period
WDCK2 WDCK1 WDCK0 Clock source Overflow period (at 10 MHz oscillation)
000
1/2
8
of the oscillation frequency
6.55ms
001
1/2
10
of the oscillation frequency
26.21ms
010
1/2
12
of the oscillation frequency
104.86ms
011
1/2
14
of the oscillation frequency
419.43ms
100
1/2
16
of the oscillation frequency
1677.72ms
1 0 1 Setting prohibited -
1 1 0 Setting prohibited -
1 1 1 Setting prohibited -