Chapter 11
Watchdog Timer
Operation XI - 9
■ Detecting Incorrect Code Execution
The watchdog timer detects error when it overflows. When the watchdog timer detects any error, the watchdog
interrupt (WD0VFIRQ) is generated as a non maskable interrupt (NMI).
Figure:11.3.2 Watchdog Operation
■ Stopping and Clearing Watchdog Timer Operation
Set the WDCNE flag of the WDCTR register to “0” to stop the watchdog timer operation.
Stop the watchdog timer operation for sure in the following case.
• Before changing the WDCK2-0 flags of the WDCTR register
Set the WDRST flag of the WDCTR register to “1” to clear the watchdog timer . Be sure to clear the watchdog
timer in the following cases.
• Before starting the watchdog timer operation
• Before changing the WDCK2-0 flags of the WDCTR register
Watchdog timer
count value
Overflow
6.55 ms to 1677.72 ms
(when the oscillation input frequency is 10 MHz)
Count reset by writing
a "1" to the WDRST flag
Non-maskable interrupt
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