Panasonic MN103S

Chapter 1
Overview
I - 12 Pin Description
1.3.3 Pin Functions
Table:1.3.2 Pin Functions
Name
TQFP 48
Pin No.
I/O Other Function Function Description
VDD
VDD
VDD
VDD
12
32
54
76
- - Power supply pin Power pins for 5 V, digital IO
Apply 5 V to all of pins and connect capacitor
of over 10 µF between all of the VDD and
VSS pins.
It is recommended that total capacitance
between all of the VDD and VSS is more than
10-times sum of capacitance between all of
the VDD2 and VSS plus capacitance etween
VDD3 and VSS.
VDD2
VDD2
33
80
- - Power supply pin Power pins for 1.8 V, digital IO
Connect capacitor of over 1 mF between all
of the VDD2 and VSS pins. .
VSS
VSS
VSS
VSS
10
29
56
78
- - Power supply pin GND for digital
VDD3 31 - - Power supply pin Power pin for 3.3 V, flash
Connect capacitor of over 2 µF between
VDD3 and VSS pins.
N, C for mask ROM version
VPPEX 30 - Power supply pin Power for flash EEPROM
Connect with VDD3.
N, C for mask ROM version
OSC1
OSC0
28
27
input
output
- Clock input pin
Clock output pin
Extend ceramic or crystal oscillators or input
a clock to OSC1.
NRST 39 input - Reset pins
(negative logic)
This pin resets the chip when power is turned
on and contains an internal pull-up resistor.
Setting this pin “L” level initializes the internal
state of the device. Thereafter, setting the
input to “H” level releases the reset. The
hardware waits for the system clock to
stabilize, and processes the reset interrupt.
Connect capacitor of over 0.1 µF between
NRST and VSS pins.
P10
P11
P12
P13
P14
P16
P17
34
35
36
37
38
40
41
I/O IRQ04
IRQ05
IRQ06
IRQ07
IRQ08
TM7IO
SBO2
I/O port 1 8-bit CMOS I/O ports.
Each bit can be set individually as either
input or output by the P1DIR register.
Pull-up resistor for each bit can be selected
individually by the P1PLU register.
At reset, the input mode (P10 to P14, P16,
P17) is selected, and pull-up resistor is
disabled.
P20
P21
P22
P23
P24
P25
P26
P27
42
43
44
45
46
47
48
49
I/O SBT2
SBI2
SBO1
SBT1
SBI1
SBO0
SBT0
SBI0
I/O port 2 8-bit CMOS I/O ports.
Each bit can be set individually as either
input or output by the P2DIR register.
Pull-up resistor for each bit can be selected
individually by the P2PLU register.
At reset, the input mode (P20 to P27) is
selected, and pull-up resistor is disabled.