Panasonic MN103S

Chapter 11
Watchdog Timer
Control Registers XI - 5
11.2.3 Watchdog Timer Control Register
The watchdog timer control register (WDCTR) is used to control the watchdog timer.
■ Watchdog Timer Control Register (WDCTR: 0x00008202) [8,16-bit Access Register]
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Before changing the values of WDCK2 to 0, stop the watchdog timer and reset the counter.
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When “1” is written to the WDRST flag, this flag generates 1 clock wide reset pulse and then changes
back to “0”. “0” is always returned when this flag is read.
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bp 76543210
Flag WD
CNE
WD
RST
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WD
CK2
WD
CK1
WD
CK0
At reset 00000001
Access R/W R/W R R R R/W R/W R/W
bp Flag Description Setting condition
7 WDCNE
Watchdog timer operation enable 0: Operation disabled (The oscillation stabilization wait operation is
possible)
1: Operation enabled
6 WDRST
Watchdog binary counter reset 0: No reset
1: Reset
5-3 - - -
2-0
WDCK2
WDCK1
WDCK0
Count clock source for Binary counter
selection
000: 1/2^8 of the oscillation frequency
001: 1/2^10 of the oscillation frequency
010: 1/2^12 of the oscillation frequency
011: 1/2^14 of the oscillation frequency
100: 1/2^16 of the oscillation frequency
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited