Panasonic MN103S

Chapter 12
Serial interface 0 and 1
Control Registers XII - 5
12.2.2 Serial Interface Reception and Transmission Registers
Serial interface 0 and 1 each 8-bit data buffer register for transmission/reception.
Data is loaded by reading data from the SCnRB register during serial reception.
Reception data can be loaded when an interrupt occurs or when the SCnRXA flag of the SCnSTR register is “1”.
In the case of 7-bit transmission, the MSB (bit 7) is “0”. Proper operation of this register is not guaranteed if data
is written. If the register is read through 16-bit access, the reception flag in the status register is cleared.
Data transmission is initiated by writing data to the SCnTB register during serial transmission.
Data transmission starts during 4 transmit clock cycles from write. In the case of 7-bit transmission, the MSB (bit
7) is ignored.
■ Serial 0 Reception Register (SC0RB: 0x0000A104) [8,16-bit Access Register]
■ Serial 1 Reception Register (SC1RB: 0x0000A114) [8,16-bit Access Register]
■ Serial 0 Transmission Register (SC0TB: 0x0000A10C) [8,16-bit Access Register]
■ Serial 1 Transmission Register (SC1TB: 0x0000A11C) [8,16-bit Access Register]
bp 76543210
Flag SCA0
RB7
SCA0
RB6
SCA0
RB5
SCA0
RB4
SCA0
RB3
SCA0
RB2
SCA0
RB1
SCA0
RB0
At reset 00000000
Access RRRRRRRR
bp 76543210
Flag SCA1
RB7
SCA1
RB6
SCA1
RB5
SCA1
RB4
SCA1
RB3
SCA1
RB2
SCA1
RB1
SCA1
RB0
At reset 00000000
Access RRRRRRRR
bp 76543210
Flag SCA
0TB
7
SCA
0TB
6
SCA
0TB
5
SCA
0TB
4
SCA
0TB
3
SCA
0TB
2
SCA
0TB
1
SCA
0TB
0
At reset 00000000
Access R/W R/W R/W R/W R/W R/W R/W R/W
bp 76543210
Flag SCA
1TB
7
SCA
1TB
6
SCA
1TB
5
SCA
1TB
4
SCA
1TB
3
SCA
1TB
2
SCA
1TB
1
SCA
1TB
0
At reset 00000000
Access R/W R/W R/W R/W R/W R/W R/W R/W