Panasonic MN103S

Chapter 5
Interrupt Controller
Overview V - 3
5.1.2 Block Diagram
■ Block Diagram of Interrupt Controller
Figure:5.1.1 Block Diagram 1
CPU core
GROUP
2
3
2
1
0
External interrupt 0
GROUP
4
3
2
1
0
GROUP
5
3
2
1
0
NMI
Level 0 to 6
GROUP
1
3
2
1
0
Reserved for system
Watchdog timer overflow (WDOVFIRQ)
System error
Timer 2 underflow
GROUP
6
3
2
1
0
GROUP
7
3
2
1
0
Timer 3 underflow
GROUP
0
3
2
1
0
Timer 6 underflow
Timer 7 underflow
Timer 8 overflow/underflow
Timer 8 compare/capture A
Timer 4 underflow
Timer 5 underflow
GROUP
4
3
2
1
0
Timer 0 underflow
Timer 1 underflow
Timer 8 compare/capture B