Panasonic MN103S

Chapter 10
Motor Control PWM
Control Registers X - 5
10.2.2 PWM Mode Control Registers
PWM mode control registers are used to set various modes for the motor control block.
■ PWM0 Mode Control Register (PWMMD0: 0x0000A300) [8,16-bit Access Register]
bp 1514131211109876543210
Flag
-
SYN
EN0
SFT
EN0
CLK
SEL
0
TMS
TA
EN0
TMS
TB
EN0
SDS
ELA
0
SDS
ELB
0
PCR
A
EN0
PCR
B
EN0
INTA
EN0
INTB
EN0
DT
EN0
OR
MD0
TC
EN0
WAV
E
MD0
At reset 0000000000000000
Access R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
bp Flag Description Setting condition
15 - - -
14 SYNEN0
Simultaneous starting function of PWM0
and PWM1 enable
0: Disabled
1: Enabled
13 SFTEN0
Output timing varying function enable 0: Disabled
1: Enabled
12 CLKSEL0
Count clock switch 0: IOCLK
1: Setting prohibited
11
TMSTAEN
0
TM12 external trigger activation enable
(PWM binary counter underflow)
0: Disabled
1: Enabled
10
TMSTBEN
0
TM12 external trigger activation enable
(PWM binary counter overflow)
0: Disabled
1: Enabled
9SDSELA0
OUTMD0 buffer mode 0: Single-buffer mode
1: Double-buffer mode
8SDSELB0
PWMSEL0 buffer mode. 0: Single-buffer mode
1: Double-buffer mode
7 PCRAEN0
Double buffer load timing enable (PWM
binary counter underflow)
0: Disabled
1: Enabled
6 PCRBEN0
Double buffer load timing enable (PWM
binary counter overflow)
0: Disabled
1: Enabled
5 INTAEN0
Timer interrupt timing enable (PWM
binary counter underflow).
0: Disabled
1: Enabled
4 INTBEN0
Timer interrupt timing enable (PWM
binary counter overflow).
0: Disabled
1: Enabled
3DTEN0
Dead Time insertion
0: No dead time
1: Dead Time
2 ORMD0
Dead Time insertion logic 0: Positive logic (H active)
1: Negative logic ( L active)
1TCEN0
PWM counting operation enable 0: Disabled
1: Enabled
0WAVEMD0
PWM waveform mode 0: Triangular wave
1: Saw-tooth wave