Panasonic MN103S

Chapter 10
Motor Control PWM
X - 6 Control Registers
■ PWM1 Mode Control Register (PWMMD1: 0x0000A330) [8,16-bit Access Register]
bp 1514131211109876543210
Flag
-
SYN
EN1
SFT
EN1
CLK
SEL
1
TMS
TA
EN1
TMS
TB
EN1
SDS
ELA
1
SDS
ELB
1
PCR
A
EN1
PCR
B
EN1
INTA
EN1
INTB
EN1
DT
EN1
OR
MD1
TC
EN1
WAV
E
MD1
At reset 0000000000000000
Access R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
bp Flag Description Setting condition
15 - - -
14 SYNEN1
Simultaneous starting function of PWM0
and PWM1 enable
0: Disabled
1: Enabled
13 SFTEN1
Output timing varying function enable 0: Disabled
1: Enabled
12 CLKSEL1
Count clock switch 0: IOCLK
1: Setting prohibited
11
TMSTAEN
1
TM13 external trigger activation enable
(PWM binary counter underflow)
0: Disabled
1: Enabled
10
TMSTBEN
1
TM13 external trigger activation enable
(PWM binary counter overflow)
0: Disabled
1: Enabled
9SDSELA1
OUTMD1 buffer mode 0: Single-buffer mode
1: Double-buffer mode
8SDSELB1
PWMSEL1 buffer mode. 0: Single-buffer mode
1: Double-buffer mode
7 PCRAEN1
Double buffer load timing enable (PWM
binary counter underflow)
0: Disabled
1: Enabled
6 PCRBEN1
Double buffer load timing enable (PWM
binary counter overflow)
0: Disabled
1: Enabled
5 INTAEN1
Timer interrupt timing enable (PWM
binary counter underflow).
0: Disabled
1: Enabled
4 INTBEN1
Timer interrupt timing enable (PWM
binary counter overflow).
0: Disabled
1: Enabled
3DTEN1
Dead Time insertion
0: No dead time
1: Dead Time
2 ORMD1
Dead Time insertion logic 0: Positive logic (H active)
1: Negative logic ( L active)
1TCEN1
PWM counting operation enable 0: Disabled
1: Enabled
0WAVEMD1
PWM waveform mode 0: Triangular wave
1: Saw-tooth wave