Chapter 6
ROM Correction
VI - 14 ROM Correction Operation
■ ROM Correction Setting Example (2)
8 bytes of data stored in the internal ROM addressees “0x40006543 ~ 0x4000654A” are corrected by ROM cor-
rection channel 0 as indicated in the following.
Lower 3 bits Before change After change
0x40006543 3 0x00 → 0x01
+1 4 0x00 0x23
+2 5 0x00 0x45
+3 6 0x00 0x67
+4 7 0x00 0x89
+5 0 0x00 0xAB
+6 1 0x00 0xCD
+7 2 0x00 0xEF
Setup Procedure Description
(1) Confirm ROM correction
RCRCTR (0x7FF00000)
bp3: RCMEN=0
bp2: RCCEN=0
bp0: RCRWE=0
(1) Confirm that the ROM correction control register
(RCRCTR) is set to “0x00” (ROM correction enable).
When it is set to “0x04” (ROM correction enabled),
reset ROM correction.
(2) Set a register write enabled
RCRCTR (0x7FF00000)
bp3: RCMEN=0
bp2: RCCEN=0
bp0: RCRWE=1
(2) Write “0x01” to the RCRCTR register to set the ROM
correction address register (RCR3AR) and the ROM
correction data register (RCR3DR) write enabled.
(3) Set the RCR3AR register
RCR3AR (0x7FF00130)
bp19-0: RC3AD19-0=0x06543
bp31: RC3CEN=1
(3) Set the lower 20 bits of the first address subject to ROM
correction in bp19~bp0 of the RCR3AR register and
theRC3CEN flag to “1” in bp31.
(4) Set the RC3DR register
RCR3DR (0x7FF00108)
=0x8967452301EFCDAB
bp63-0: RC3DT63-0
=0x8967452301EFCDAB
(4) Set 8 bytes of data (0x8967452301EFCDAB) used for
ROM correction to the RCR3DR register.
(5) Set ROM correction enabled (5) Write “0x04” to the RCRCTR register to enable ROM
correction.
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