Chapter 5
Interrupt Controller
V - 14 Control Registers
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When using LV2 to 0 bits or IE3 to 0 bits in the group n interrupt control register (GnICR) to
set the interrupt priority level or specify whether to enable interrupts, make sure that inter-
rupts are disabled as indicated below.
and 0xf7ff,psw ; Clears IE in the PSW
nop ; Insert to guarantee that IE has been definitely cleared in the pipeline fashion
nop ;
mov d0,(GnICR); Changes LV2 to 0 and IE3 to 0
mov (GnICR),d0; Inserted for synchronizing with the store buffer
or 0x0800,psw ; Set IE in the PSW
However, during the execution of the interrupt handler, IE in the PSW=0 unless it is set;
therefore, it is not necessary to clear IE for disabling interrupts.
The nop instruction shown above can be any instructions provided that they do not change
the IE in the PSW or change LV2 to 0 and IE3 to 0 in the GnICR.
In addition, the nop instruction is inserted twice to positively provide the “minimum” number
of cycles required to change the IE in the PSW. Therefore, more than two nop instructions
may be inserted.
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