Panasonic MN103S - Page 213

Chapter 8
8-bit Timer
Control Registers VIII - 23
■ Timer 5 Mode Register (TM5MD: 0x0000A1A1) [8-bit Access Register]
bp 76543210
Flag TM5
CNE
TM5
LDE
---TM5
CK2
TM5
CK1
TM5
CK0
At reset 00000000
Access R/W R/W R R R R/W R/W R/W
bp Flag Description Set condition
7 TM5CNE
Timer operation enable 0: Operation disabled
1: Operation enabled
6TM5LDE
Timer initialization 0: Normal operation
1: Initialization
TM5BR value is loaded into TM5BC. Timer output 5 is set to “L” level.
5-3 - - -
2-0
TM5CK2
TM5CK1
TM5CK0
Count clock source selection 000: IOCLK
001: IOCLK/8
010: IOCLK/32
011: Cascading with timer 4
100: Timer 4 underflow[
101: Setting prohibited
110: Timer 6 underflow
111: TM5IO pin input (rising edge)
When 1/8 IOCLK or 1/32 IOCLK are used, the prescaler control regis-
ter (TM47PSC) should be set.