Chapter 8
8-bit Timer
Control Registers VIII - 25
■ Timer 7 Mode Register (TM7MD: 0x0000A1A5) [8,16-bit Access Register]
bp 76543210
Flag TM7
CNE
TM7
LDE
---TM7
CK2
TM7
CK1
TM7
CK0
At reset 00000000
Access R/W R/W R R R R/W R/W R/W
bp Flag Description Set condition
7TM7CNE
Timer operation enable 0: Operation disabled
1: Operation enabled
6TM7LDE
Timer initialization 0: Normal operation
1: Initialization
TM7BR value is loaded into TM7BC. Timer output 7 is set to “L” level.
5-3 - - -
2-0
TM7CK2
TM7CK1
TM7CK0
Count clock source selection 000: IOCLK
001: IOCLK/8
010: IOCLK/32
011: Cascading with timer 6
100: Timer 4 underflow[
101: Timer 5 underflow
110: Timer 6 underflow
111: TM7IO pin input (rising edge)
When 1/8 IOCLK and 1/32 IOCLK are used, the prescaler control reg-
ister (TM47PSC) should be set.
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