Chapter 8
8-bit Timer
VIII - 46 Cascade Connection
TM1BC+TM0BC counter counts down as a 16-bit counter.
When TM1BC+TM0BC counter generates the underflow, the interrupt request flag (G3IR1) is set and the value
of TM1BR and TM0BR register is loaded to TM1BC and TM0BC counter; and, the counter starts to count down
again.
(8) Start the timer operation
TM1MD(0x0000A181)
bp7: TM1CNE=1
TM0MD(0x0000A180)
bp7: TM0CNE=1
(8) Set the TM1CNE flag of the TM1MD register to “1” to
operate the timer 1 of the upper timer. Set the TM0CNE
flag of the TM0MD register to “1” to operate the timer 0.
Setup Procedure Description
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