Chapter 9
16-bit Timer
Control registers IX - 25
■ Timer 13 Mode Register (TM13MD: 0x0000A2A0) [8, 16-bit Access Register]
bp 1514131211109876543210
Flag TM
XF
-TM
TGE
TM
ONE
TM
CLE
TM
CGE
TM
UD1
TM
UD0
TM
CNE
TM
LDE
---TM
CK2
TM
CK1
TM
CK0
At reset 0000100000000000
Access R R R/W R/W R/W R/W R/W R/W R/W R/W R R R R/W R/W R/W
bp Flag Description Setting condition
15 TMXF
Timer operation display 0: Timer stopping
1: Timer operating
14 - - -
13 TMTGE
Timer external trigger enable 0:Timer activation disabled by PWM1
1: Timer activation enabled by PWM1
When timer activation is enable by PWM1, set the activation trigger
polarity selection of the timer 13 compare A mode register to “1”.
12 TMONE
Timer 1-shot operation enable 0 : 1-shot operation disabled (Timer does not stop.)
1: 1-shot operation enabled (Timer stops when the TMBC and the
TMCA match.)
11 TMCLE
Timer binary counter enable 0: Clear operation disabled
1: Clear operation enabled
When the TMCA is set to a compare register
TMBC is cleared when the TMBC and the TMCA match.
When the TMCA is set to a capture register
TMBC is cleared when captured to TMCA.
10 TMCGE Reserved Always set to “0”
9-8
TMUD1
TMUD0
Up/down counting selection 00: Up counting
01: Down counting
10: Setting prohibited
11: Setting prohibited
7 TMCNE
TImer operation enable 0: Operation disabled
1: Operation enabled
6TMLDE
Timer initialization 0: Normal operation
1: Initialization
TMBC=0x0000
When the TMCA and TMCB are set to the compare register of the
double buffer, the value is loaded into the compare register from the
buffer. Pin output is initialized.
5-3 - - -
2-0
TMCK2
TMCK1
TMCK0
Timer count clock source selection 000: IOCLK, MCLK
001: IOCLK/8, MCLK/8
010: Timer 6 underflow
011: Timer 7 underflow
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
When using IOCLK/8, operation must be enabled by the prescaler
control registers (TMPSCNE).
When using MCLK, select MCLK by the clock source selection reg-
ister ( TMnCLK).
To Next Page
Loading...
