Panasonic MN103S

Chapter 9
16-bit Timer
Control registers IX - 35
■ Timer 11 Compare/Capture B Mode Register (TM11MDB: 0x0000A265) [8-bit Access Register]
bp 76543210
Flag TM
BM1
TM
BM0
TM
BEG
TM
BCE
--TM
B01
TM
B00
At reset 00000000
Access R/W R/W R/W R/W R R R/W R/W
bp Flag Description Setting condition
7-6
TMBM1
TMBM0
Timer compare/capture B operation
mode selection
00: Compare register (double buffer)
01: Compare register (single buffer)
10: Capture register ( single-edge operation)
Capture at the edge selected by timer B pin polarity selection bit.
11: Capture register ( both-edge operation)
Selection by timer B pin polarity selection is ignored.
5 TMBEG
Timer B pin polarity selection 0 Capture Rising edge (when single edge is
selected)
Count source Rising edge (when single edge is
selected)
Pin output Positive polarity output
“L” level when reset, “H” level when
set
1 Capture Falling edge (when single edge is
selected)
Count source Falling edge (when single edge is
selected)
Pin output Negative polarity output
“H” level when reset, “L” level when
set
4TMBCE
Timer capture B operation enable 0: Capture operation disabled (pin input is ignored)
1: Capture operation enabled
3-2 - - -
1-0
TMB01
TMB00
Timer B output waveform selection 00: Set when TMBC and TMCB match, reset when TMBC and
TMCA match
01: Set when TMBC and TMCB match, reset when TMBC overflows
10: Set when TMBC and TMCB match (reset only when timer is ini-
tialized)
11: Timer output (output is inverted when TMBC and TMCB match)