Chapter 9
16-bit Timer
IX - 44 Event Count
■ Count Timing of Event Count Operation
TMnBIN pin input is sampled by IOCLK. The edge selected by the TMnBIN pin input is counted, and the binary
counter counts up. The pulse width should be IOCLK × 1.5 or more for detecting the edge. Table: 9.5.4 shows
operation condition and Figure: 9.5.1 the count timing.
Table:9.5.4 Operation Condition
Figure:9.5.1 Count Timing of Event Count Operation
■ Setting the Count Control Input
The count clock of the binary counter can masked based on the input level of the TMnMAIN pin. The timer count
control input is enabled by setting the TMCGE flag of the timer mode register (TMnMD) to “1”. The input level
for masking is set by the TMAEG flag of the timer compare/capture A mode register (TMnMDA). Table: 9.5.5
shows the relationship between the input level and TMAEG flag.
Table:9.5.5 Input Level and TMAEG flag
Operation condition Setting description
Input edge Rising edge
Timer up/down selection Up counting
Timer compare/capture A operation mode selection Compare register (single buffer)
Timer counter clear enable Clear operation enabled
TMnAIN pin
TMAEG flag (TMnMDA register)
01
"H"
Normal operation
(counting)
Count clock masked
(stop counting)
"L"
Count clock masked
(stop counting)
Normal operation
(counting)
Pin input
(TMnBIN)
TMLDE
flag
TMCNE
flag
IOCLK
Sampling Sampling Sampling
0000 00000001 N-1 N
N
Compare/capture
register
Binary counter
Interrupt
request flag
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